Integrated circuit fabrication typically begins with a thin, polished slice of high-purity, single crystal semiconductor material, usually silicon. Junctions (which make up devices) are formed between field oxide portions of the semiconductor slice. Metal lines in conductor layers provide necessary electrical connections between the devices. Dielectric (i.e. insulating) layers are formed between the conductor layers to isolate the metal lines from each other. Vias provide conducting paths through the dielectric layers to connect the interconnects of different conductor layers.
As micro-miniaturization of integrated circuits has increased, the smaller features have presented challenges to the semiconductor fabrication engineer. For example, the vias for connecting the interconnects are normally designed to be fully landed on the underlying structure. However, allowing only fully landed openings on increasingly narrow metal features results in extremely small contact or via holes. This in turn can result in very difficult via lithography and increased contact or interface resistance between all of the overlying metal structure and the underlying interconnect structure due to the decreased contact area. Borderless vias, which are not required to fully land on the underlying structure, have therefore found acceptance in the semiconductor industry due to their larger size and decreased resistance.
In high performance integrated circuits in the sub-0.25 .mu.m regime, there is a need to fabricate interconnects using so-called damascene techniques. This is because conventional deposition and etching of aluminum-based metalization becomes increasingly difficult at these feature sizes. At the same time, performance considerations call for the use of lower resistivity metals such as copper, which has proven extremely difficult to pattern using conventional reactive ion etching. The desire to use copper for interconnects has increased the attractiveness of damascene techniques and spurred investigation into improving these techniques.
In addition to using low resistivity metals such as copper, circuit performance enhancement has been sought by combining the copper conductors with low dielectric constant insulators (k less than approximately 4). In many cases, these low k materials are spin-coated polymers which are incompatible with conventional photoresist stripping using oxygen ashers or solvents. The patterning of the low k materials to form the trenches and vias of a damascene structure is a difficult task due to the incompatibility of the low k materials with conventional photoresist stripping. The difficulties in patterning are exacerbated if the vias are allowed to be the borderless type.
An example of a dual damascene process sequence using a low k dielectric, having trenches with underlying via holes that are etched in the low k dielectric material before metal deposition and chemical-mechanical polishing (CMP), is depicted in FIGS. 1A-1D. This commonly used method of forming the trenches together with the via holes employs etch stop layers and photoresist masks. A bottom stop layer 14, such as silicon nitride, has been deposited over an existing interconnect pattern formed in an interconnect layer 10. The interconnect pattern may be formed from a conductor 12, such as copper. A layer of low k material 16 is then deposited on the bottom stop layer. The via will be formed within this low k dielectric layer 16.
A middle stop layer 18, such as silicon dioxide, is deposited over the low k dielectric layer 16. A via pattern 20 is etched into the middle stop layer 18 using conventional photolithography and appropriate anisotropic dry etching techniques. (These steps are not depicted in FIG. 1A. Only the resultant via pattern 20 is depicted in FIG. 1A.) The photoresist used in the via patterning is removed by an oxygen plasma, which consumes some of the exposed low k material, as indicated in FIG. 1A.
FIG. 1B depicts the structure of FIG. 1A after a second layer of low k dielectric material has been spin-coated on the middle stop layer 18 and through the via pattern opening 20. Due to the nature of spin-coated materials, the structure is planarized at the same time. Following the spin-coating and the planarization of the low k dielectric layers 22, in which the trench will be formed, a hard mask layer 24 is deposited. The hard mask layer 24 may be silicon dioxide, for example.
The trench pattern is then formed in a photoresist layer (not depicted) which is aligned over the via pattern, using conventional photolithography. The structure is then exposed to an anisotropic dry etch configured to etch through the hard mask layer 24. The etch chemistry is then changed to one which selectively etches the low k dielectric material in the low k dielectric layers 22 and 16, but not the hard mask layer 24 nor the middle and bottom stop layers, 18 and 14. In this way, a trench 26 and a via 28 are formed in the same etching operation.
In most cases, the low k etch chemistry etches the photoresist at approximately the same rate as the low k dielectric. The thickness of the trench photoresist is selected to be completely consumed by the end of the etch operation, to eliminate the need for photoresist stripping. This results in the structure depicted in FIG. 1C, in which all of the photoresist has been stripped and the trench 26 and via 28 have been formed. The bottom stop layer 14 is then removed by a different selective dry etch chemistry designed not to attack any other layers in order to expose conductor 12 to which the via is making a connection. The resulting structure is depicted in FIG. 1D. The bottom stop layer is normally used to protect the pre-existing interconnect layer from oxidation or corrosion during dry etching. If such concerns do not exist, bottom stop layer 14 and the corresponding bottom stop layer etching step is omitted.
The processing sequences depicted in FIGS. 1A-D are adequate if a sufficient overlay margin between the trenches and the vias is designed in the process to guarantee that the via openings will never fall outside the trench openings with the expected amount of overlay error. However, beginning with the 0.25 .mu.m generation of integrated circuits, the overlay accuracy of photolithography equipment becomes a significant fraction of the minimum feature size. As a result of circuit compactness considerations, situations where the overlap between the conductor lines and vias is smaller than the expected alignment accuracy must be allowed. These vias are described as "borderless" or "unlanded", and are allowed to "fall off" the lower and upper conductor lines due to the expected alignment limitations, to the extent that unintentional short circuits can still be avoided.
FIG. 2 depicts a dual damascene structure in which a borderless via has been misaligned during the dual damascene trench and via formation in low k dielectrics. In dual damascene processing sequences that use a buried stop layer, such as the stop layer 18 in FIGS. 1A-1D, a via hole opening 30 etched in stop layer 18 that partially falls outside the trench opening 26 over it due to misalignment will result in a reduction in the final via size. This is due to the anisotropic etching of the low k dielectric material in the two low k dielectric layers being performed only in accordance with the intended trench opening in the hard mask layer 24. The area of the via opening 30 that does not fall within the trench opening due to misalignment will not be etched resulting in a smaller-sized via 32. Since the final size of the via 32 has thus been reduced, the via resistance is increased. The reduction in the final via size also makes it more difficult to achieve good barrier metal step coverage and void-free conductor filling.